Semiconductor devices such as Ball Grid Array (“BGA”) packages are usually small in size and are transported and/or processed in batches so as to increase operation efficiency. Thus, they are often loaded in a carrier in array form for transportation and processing. Examples of processes carried out on BGA packages arranged in array form include solder paste printing, solder balls attaching and testing. Processing of several or all semiconductor devices in a carrier simultaneously results in high throughput, but that in turn requires precise alignment of the devices in the carrier prior to processing. Poor alignment of the devices will directly affect the yield of processes subsequent to alignment. Alignment capability and accuracy becomes even more critical for fine pitch devices.
Various approaches have been implemented in the prior art to align semiconductor devices on carriers. In a cavity approach, a guiding plate with a cavity opened for receiving a semiconductor device is used for aligning it with respect to edges of the device. In U.S. Pat. No. 5,688,127 entitled “Universal Contactor System for Testing Ball Grid Array (BGA) Devices on Multiple Handlers and Method Therefor”, a cavity approach is described wherein a guide plate has a cavity that is adapted to receive a BGA package for alignment. The opening size of the cavity is reduced gradually from the device entrance point to the inner portion of the cavity. The BGA package is guided by the narrowing opening and is aligned with the interior walls of the cavity at the inner portion.
A problem with this approach is that a clearance must exist between the BGA package and interior walls of the cavity to avoid jamming of the device. Also, additional clearance should be added to accommodate any variation in sizes of different BGA packages resulting from a prior singulation process. The resultant clearance between the BGA package and cavity may result in poor alignment. Furthermore, the guiding interaction between the interior walls of the cavity and BGA packages may cause potential tilting or dislocation of packages especially if the initial misalignment is large.
Alternatively, in a pin approach, two or more pins are used to align semiconductor devices with respect to a carrier, with apertures formed in both the devices and the carrier for the pins to pass through for alignment. The pin approach to align semiconductor devices with respect to a carrier is described in U.S. Pat. No. 6,338,297 entitled “Precise and Rapid Positioning Mechanism for Stencil Printing” and US patent publication number 2003/042626A1 entitled “Method of Ball Grid Array (BGA) Alignment, Method of Testing, Alignment Apparatus and Semiconductor Device Assembly”. According to the pin approach, two or more apertures are formed in each semiconductor device, with the carrier having the same pattern of apertures at each landing site for the semiconductor devices. Apertures in the semiconductor devices and carrier are pre-aligned, with pins passing through the apertures of both parts to assist alignment.
This approach has the shortcoming that holes have to be formed in the semiconductor devices, which reduces the area available for placing input/output connections. Also, the holes reduce the area available for a suction cup to pick up the devices during pick-and-place operations using vacuum suction. Another shortcoming is that unless the pins and apertures in both semiconductor devices and carriers have minimal clearance, precise alignment cannot be achieved. However, it becomes very difficult, if not impossible, to align a plurality of semiconductor devices with the carrier by automated means if the pins and apertures are of similar size so that they fit tightly. This may require manual alignment that is not preferable for high volume production. Even if automated means can be applied, the striking of the pins into corresponding apertures of unaligned semiconductor devices may cause potential tilting or dislocation.